1. Field of the Invention
The present invention relates to a method of dielectric planarization. More particularly, it relates to an etch-back method of an inter-layer dielectric (ILD) or an inter-metal dielectric (IMD) planarization.
2. Description of the Related Art
Presently, a popular trend in integrated circuits (ICs) are ICs with high integration, wherein more and more dielectric or metal layers are integrated on a substrate to form devices, affecting the overall uniformity of the substrate. Substrates with poor uniformity encounter poor resolution or insufficient depth of focus (DOF) in subsequent photolithography.
In conventional ICs fabrication, devices such as MOS transistors or patterned metal lines are formed on a substrate first, a layer of dielectric is deposited on and between the devices, and another metal layer is then deposited. The dielectric layer used as an insulating layer between metal lines and devices is referred to as an inter-layer dielectric (ILD), with the dielectric layer used as an insulating layer between metal lines in different layers referred to as an inter-metal dielectric (IMD).
The ILD or IMD dielectric layer is conventionally a silica-based oxide layer, such as silicon dioxide or doped silicon dioxide, e.g. BSG, BPSG or PSG, or oxygen-containing low-k dielectric materials, e.g. SiOC or SiOF, developed recently.
The deposited dielectric layer conforms to the patterned substrate, so conventional chemical mechanical polishing (CMP) is performed to planarize the surface of the dielectric layer, and then a planarized dielectric layer on the substrate is provided and subsequent photolithography can be easily performed.
FIGS. 1 and 2 are cross sections of inter-layer dielectric (ILD) devices on a substrate before and after CMP planarization. In FIG. 1, a substrate 10, for example, silicon, is provided with a plurality of devices D is in a dense area 20 and in a sparse area 40 on the substrate 10. Devices D are maybe MOS transistors, capacitors or other logic devices, and the surfaces of devices D are an oxygen-free material, such as silicon nitride (Si3N4), poly-silicon, amorphous silicon, metal or metal nitride. A dielectric layer 12 is formed, blanketing on and between devices D in areas 20 and 40. The dielectric layer 12 is made of an oxygen-containing material, such as silicon dioxide, doped silicon dioxide (for example, BSG, BPSG or PSG), or oxygen-containing low-k materials (for example, SiOC or SiOF). The formed dielectric layer 12 with a thickness exceeding the height of devices D is taken as an inter-layer dielectric (ILD) between devices D to insulate the devices D from each other.
In FIG. 2, a conventional chemical mechanical polishing (CMP) process achieves overall planarization of the ILD layer 12. Due to frequent difficulties in determining the end-point of the polishing process, the dishing in sparse area 40 occurs, as does over-polishing in the dense area 20, and the conformation and structure of the devices D maybe damaged. After CMP, the planarized ILD layer 12 has a thickness difference H1 between 300xcx9c800 angstrom in the dense area 20 and the sparse area 40. The uniformity of the planarized ILD layer 12 in FIG. 2 is thus poor, and the results of planarization are affected.
Thus, an ILD layer may be formed on a substrate with devices unequally spaced thereon, wherein spacing is dense in some areas, and sparser in others. When CMP is performed to planarize the ILD layer on the substrate, dishing often occurs in the sparsely populated areas. In the densely populated areas, overpolishing caused by the dishing also occurs, possibly damaging the device. Thus, after CMP, the ILD layer is usually left with a thickness difference of 300 angstroms above or below the devices nearby (the maximum can be even 1600 angstroms). The overall uniformity of the ILD layer after CMP is poor, with the surface of the ILD layer not planarized.
Hence, there is a need for a better method to solve the uniformity issue after planarization.
Accordingly, an object of the invention is to provide an etch-back method for the dielectric layer planarization that results in better surface uniformity.
Etching gases often contain the fluorocarbon compound (CXFY), from the CF4-containing etching gas used in the past to the C2F6- or C3F8-containing gases used recently as a source of carbon atoms and fluorine atoms. During etching of silicon dioxide, oxygen atoms are formed as byproducts of the etching process. Once the ambient concentration of oxygen atoms drops, the etching process is near the end, and the end-point of the etching process can be determined by monitoring the concentration of the oxygen atoms through the sensors attached to an etching apparatus.
Generally speaking, two phases occur during dry etching, etching, and deposition. In the etching phase, the etched parts are driven out, and in deposition, a protection layer is deposited to prevent subsequent etching.
Another object of the etch-back method of the invention is to precisely control the ratio of the etching gas (mainly C5F8 and CHF3 in the invention). In the process, when devices or patterned metal lines on a substrate are still covered by oxygen-containing ILD or IMD, the concentration of oxygen remains steady, and the process is still in the etching phase. When the material covering the devices or the patterned metal lines is etched out and the devices and the metal lines are exposed, the concentration of oxygen atoms drops, the etching enters the deposition phase, and a layer of hydrofluorocarbon polymer with a thickness within a hundred angstroms is deposited as a protection layer. The deposition rate of the protection layer is balanced to the decreasing oxygen concentration. Once the oxygen concentration decreases, the reaction enters the deposition phase, and finally the oxygen concentration is low enough that etching stops automatically.
The process of ILD planarization of the invention comprises providing a substrate with devices formed in varying areas of density, forming a blanket dielectric layer between and on the devices in all areas, and performing a reactive ion etching (RIE) such that the dielectric layer is etched with a gas comprising C5F8 and CHF3, stopping on the devices, such that, finally, a uniform dielectric layer is provided.
The process of IMD planarization of the invention comprises providing a substrate with a plurality of patterned metal lines thereon, forming a blanket dielectric layer between and on the metal lines, and reactive ion etching (RIE) at a pressure between 35xcx9c85 milliTorr with operating AC power between 1100xcx9c1900 W applied. The dielectric layer is etched with a gas comprising C5F8 and CHF3, stopping on the devices, such that a uniform dielectric layer is provided between the patterned metal lines in all areas.
A detailed description is given in the following embodiments with reference to the accompanying drawings.